供应4Mb存储器ic芯片同步快速

?VDD = 2.5V(2.3V ~ 2.7V) or 3.3V(3.1V ~ 3.5V) Power Supply

?VDDQ = 2.3V~2.7V I/O Power Supply (VDD=2.5V) or 2.3V~3.5V I/O Power Supply (VDD=3.3V)

?Synchronous Operation

?Self-Timed Write Cycle

?On-Chip Address Counter and Control Registers

?Byte Writable Function

?Global Write Enable Controls a full bus-width write

?Power Down State via ZZ Signal

?LBO Pin allows a choice of either a interleaved burst or a lin- ear burst

?Three Chip Enables for simple depth expansion with No Data Contention only for TQFP

?Asynchronous Output Enable Control

?ADSP, ADSC, ADV Burst Control Pins

?TTL-Level Three-State Output

?Operating in commeical and industrial temperature range

?100-TQFP-1420A (Lead free package)

The S7B403635M and S7B401835M are 4,718,592-bit Synchro- nous Static Random Access Memory designed for high perfor- mance.

It is organized as 128K(256K) words of 36(18) bits and inte- grates address and control registers, a 2-bit burst address counter and added some new functions for high performance applications; GW, BW, LBO, ZZ. Write cycles are internally self- timed and synchronous.              

Full bus-width write is done by GW, and each byte write is per-

formed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals.

Burst cycle can be initiated with either the address status pro-

cessor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the sys- tem’s burst sequence and are controlled by the burst address advance(ADV) input.

LBO pin is DC operated and determines burst sequence(linear or interleaved).

ZZ pin controls Power Down State and reduces Stand-by cur- rent regardless of CLK.

The S7B403635M and S7B401835M are fabricated using high

performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to

minimize ground bounce.