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1k * 13 bits on-chip ROM
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48 * 8 bits on-chip registers (SRAM, general purpose)
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5 level stacks for subroutine nesting
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3 programmable level voltage reset
LVR : 4.0, 3.5, 2.7V
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Less than 1.5 mA at 5V / 4MHz
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Typically 15 μA at 3V / 32kHz
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Typically 1 μA during Sleep mode
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2 bidirectional I/O ports : P5, P6
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12 I/O pins
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Wake-up port : P6
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7 Programmable pull-down I/O pins
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8 programmable pull-high I/O pins
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8 programmable open-drain I/O pins
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2 programmable R-option pins
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External interrupt : P60
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2.1V ~ 5.5V at 0 ~ 70(C (Commercial)
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2.3V ~ 5.5V at -40 ~ 85(C (Industrial)
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Operating frequency range(base on 2 clocks)
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Crystal mode:
DC ~ 20MHz / 2clks @ 5V
DC ~ 8MHz / 2clks @ 3V
DC ~ 4MHz / 2clks @ 2.1V
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IRC mode:
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